The semiconductor or integrated circuit (IC) industry constantly strives to manufacture ICs with higher and higher densities of devices on a smaller chip area to achieve greater functionality and to reduce manufacturing costs. This drive for large scale integration has led to a continued shrinking of circuit dimensions and device features. However, as device features become smaller, required device performance and functionality have increased. For example, capacitors, which are typical devices integrated into ICs, are becoming smaller and smaller but still need to have a high capacitance.
A vertically stacked, intralevel interdigitated metal capacitor may be formed to filter out noise in a circuit. The capacitor must have a low resistance and high reliability. As the dimensions of the capacitor are reduced, the charge storage of the capacitor is also decreased. To improve the electrical conductivity of the metal capacitor, efforts have been made to form dense vias connecting metals on both nodes of the capacitor, as illustrated in FIG. 1, wherein vertical lines 101 alternate with lines 103, forming a comb structure. Similarly, horizontal lines 105 alternate with lines 107 to form a second comb structure. Vias 109 interconnect lines 101 and 105, and vias 111 interconnect lines 103 and 107. As such, lines 101 and 105 are wired together and connected to a positive voltage outside the comb, thereby forming a first net, and lines 103 and 107 are wired together and connected to a negative voltage outside the comb, thereby forming a second net.
Trenches for the metal lines and integral holes for the vias are typically formed by a dual damascene process. As a result, the vias have a tapered profile, in which the top of the via is larger than the trench, thereby reducing the space between the via and neighboring metal lines of a different net and between vias of different nets. If the space becomes too small, leakage and shorts occur. In addition, it is difficult to control the via profile, which causes reliability issues.
To avoid shorts, the space between adjacent metal lines may be increased. However, an increase in spacing expands the total area of the capacitor and decreases the capacitance per unit area (the capacitance density).
To improve reliability, efforts have been made to form vias only on metal lines of one of the two nodes. As illustrated in FIG. 2, wide vertical lines 201 alternate with narrow vertical lines 203, and wide horizontal lines 205 alternate with narrow lines 207. Lines 201 are interconnected with lines 205 through vias 209, and each of lines 201 and 205 is connected to one potential (e.g. a positive voltage (not shown)). However, lines 203 and 207 are only connected to each other and to a different potential (e.g. a negative voltage) at their line ends, at 211. By decreasing the width of lines 203 and 207 and not forming vias with the narrow lines, metal-to-metal spacing can be maintained, and via to metal spacing is increased. However, although this type of design improves reliability, it reduces the via density, particularly that of lines 203 and 207, thereby degrading electrical connection. In addition, the narrow lines have a higher resistance, thereby introducing a significant intrinsic resistance into the chip, particularly when the capacitor size is large.
A need therefore exists for a metal capacitor with improved reliability while maintaining good conductivity for both nodes of the capacitor.